1. Field of the Invention
This invention relates to a semiconductor memory device, especially relates to an electrically rewritable and non-volatile memory (EEPROM).
2. Description of Related Art
A NAND-type flash memory is known as one of EEPROMs. In the NAND-type flash memory, a memory cell array is formed of NAND cell units with a small unit cell area, in which plural memory cells are connected in series to constitute a NAND cell unit. Therefore, the memory capacitance may be easily increased in comparison with a NOR-type flash memory.
Recently, to achieve a large capacitive NAND-type flash memory, there have been provided various kinds of multi-value storage schemes, in each of which one memory cell store two or more bits (for example, refer to Unexamined Japanese Patent Application Publication No. 2001-93288, or Unexamined Japanese Patent Application Publication No. 2000-195280).
At a data read time of the NAND-type flash memory, a selected word line in a selected NAND block is applied with a read voltage, which turns on or off the selected cell in accordance with cell data; and non-selected word lines are applied with a read pass voltage, Vread, which turns on cells without regard to cell data. With this voltage application, a sense amplifier detects whether the selected cell is on or off via a bit line, thereby sensing data.
In the conventional flash memory, data is defined by memory cell's threshold voltage level. Therefore, in case of a multi-value data storage scheme, various threshold levels are used. While it is in need of setting the above-described read pass voltage Vread to be higher than the uppermost one in the threshold levels to be set in a cell, as the number of threshold levels is increased more, data margin between cell threshold levels, and a margin between the highest threshold level and the read pass voltage become less.
Therefore, it is required to control multi-value data write in such a manner that the highest threshold level is certainly lower than the read pass voltage Vread. Especially, it is difficult to control the written threshold levels in the write scheme described in Unexamined Japanese Patent Application. Publication No. 2001-93288, which includes such a write step as to boost the lowest threshold level to the highest threshold level.